====== Základy tvorby aplikací pro HC08 v prostředí CodeWarrior, komunikace přes SCI ======
<code m68k>
;**************************************************************
;* Ukol c.1 pro laboratore IMP
;**************************************************************

 
; export symbols
            XDEF Entry        ; exportuj 'Entry' symbol
            ABSENTRY Entry    ; navesti, kde zacina aplikace
           
; prihrej definice zvoleneho mikrokontroleru 
            Include 'derivative.inc'

VectorStart EQU  $FFDA  ; zacatek tabulky prerusovacich vektoru

; Misto pro promenne a data
            ORG RAMStart

text	  ds.b	64

; Misto pro program
            ORG ROMStart


;**************************************************************
;* Entry - Tady se zacne provadet kod po resetu procesoru     *
;*                                                            *
;**************************************************************
Entry:
       rsp
       clra                ; Inicializace A,X
       clrx
       clrh

       mov #$01,CONFIG1    ; Vypnout COP
       jsr Init_SCI        ; Inicializace SCI
       cli                 ; Povoleni preruseni

;hlavni smycka programu		

main_loop:
;Sem doplnte kod, ktery bude cist znaky z SCI. Kazdy precteny
;znak zpracujte a provedte prislusne akce dle pokynu v zadani 
  bsr Receive_char
    sta text,X
    incx
    cbeqx #64, kon ;precetl jsem 64 znaku
    cbeqa #27, kon ;ESC
    cmp #97 ;a
      bge toupper
    cmp #90 ;Z
      ble tolower
      
  ;bsr Send_char
  ;bra kon
	bra		main_loop
	
toupper:
  sub #32
  bsr Send_char
  bra main_loop
  
tolower:
  add #32
  bsr Send_char
  bra main_loop

kon:

       bset    1,DDRA         ; PTA1 vystup (pipatko)
beep_loop:
       ldx     #$FF
dela1:
       nop
       nop
       nop
       nop
       dbnzx   dela1
       lda     #2
       eor     PTA            ; beep je potreba generovat frekvenci cca 1kHz
       sta     PTA
       brclr   5,SCS1,beep_loop ; prisel znak z SCI?
       lda     SCDR           ; precteni 
       bclr    1,DDRA         ; PTA1 vstup (a je klid)

idle:	bra	idle

;*********************************
;* Init_SCI - inicializuj SCI    *
;*********************************
Init_SCI:
       mov   #$A2,SCBR       ; Baud Rate = 9600 @ 9,8MHZ-BUS CLK
       mov   #$40,SCC1       ; povol SCI periferii
       mov   #$0C,SCC2       ; povol SCI prijimac a vysilac
       clr   SCC3            
       rts

;**************************************************************
;* Receive_char - prijmi znak z SCI vstupu a uloz jej do A    *
;**************************************************************
Receive_char:
;Zde doplnte kod pro prijem znaku z SCI.
;Rutinka bude cekat, dokud se v datovem registru SCI neobjevi
;novy znak. Pak vrati tento znak v registru A.
        brclr 5,SCS1,*
        lda SCDR
        rts

;**************************************************************
; Send_char - znak z A posli na SCI vystup		                *
;**************************************************************
Send_char:
        brclr   7,SCS1,*        ; cekej dokud je SCI vysilac busy
        sta     SCDR            ; neni -> muzeme poslat nas znak
        rts

;**************************************************************
;* spurious - obsluha pro nevyuzivana preruseni		      *
;**************************************************************
spurious:		
            NOP		
            RTI

;**************************************************************
;*                 tabulka prerusovacich vektoru              *
;**************************************************************
        ORG  VectorStart
        ; routine	  ; popis vektoru           	;adresa vektoru
        fdb  spurious     ; Real-time Clock Vector   	;$FFDA
        fdb  spurious     ; ADC Conversion Complete  	;$FFDC
        fdb  spurious     ; Keyboard Vector		;$FFDE
        fdb  spurious     ; SCI Transmit Vector		;$FFE0
        fdb  spurious     ; SCI Receive Vector		;$FFE2
        fdb  spurious     ; SCI Error Vector		;$FFE4
        fdb  spurious     ; SPI Receive Vector		;$FFE6
        fdb  spurious     ; SPI Transmit Vector		;$FFE8
        fdb  spurious	    ; TIM2 Overflow Vector	;$FFEA
        fdb  spurious     ; TIM2 Channel 1 Vector	;$FFEC
        fdb  spurious     ; TIM2 Channel 0 Vector	;$FFEE
        fdb  spurious     ; TIM1 Overflow Vector	;$FFF0
        fdb  spurious     ; TIM1 Channel 1 Vector	;$FFF2
        fdb  spurious     ; TIM1 Channel 0 Vector	;$FFF4
        fdb  spurious     ; PLL Vector			;$FFF6
        fdb  spurious     ; LVI Vector			;$FFF8
        fdb  spurious     ; ~IRQ1 Vector		;$FFFA
        fdb  spurious     ; SWI Vector			;$FFFC
        fdb  Entry        ; Reset Vector		;$FFFE
</code>